1. Field of the Invention
The invention relates to an electrostatic discharge protection circuit, and in particular to an electrostatic discharge protection circuit with a shallow trench isolation (STI) structure.
2. Description of the Related Art
In or after semiconductor process for ICs, such as DRAMs and SRAMs, electrostatic discharge is usually a main factor to break down the ICs. For example, people who walk through a rug can be detected having several hundreds to thousands volts of electrostatic charges attached thereon in a higher relative humility environment, and even having more than ten thousand volts of electrostatic charges in a lower relative humility environment. When the electrostatic charges attached happen to contact a chip, the electrostatic charges can be discharged to cause the chip malfunction. In order to protect the chip against damage from an electrostatic discharge, a variety of methods has been developed. In a most common prior method, a hardware is used to prevent damage caused by an electrostatic discharge. That is, an on-chip electrostatic discharge protection circuit is designed between an internal circuit and each pad for protecting the internal circuit from damage.
Furthermore, in line with the increase of integration in semiconductor process, the thickness of a gate oxide layer is decreased. This causes the breakdown voltage of the gate oxide layer increasingly close to or even be lower than that on the junction of source/drain. Therefore, the performance of the designed electrostatic discharge protection circuit becomes much poorer. Most of internal circuits are designed based on a minimum design rule regardless of strong transient currents which could be caused by electrostatic discharges. In other words, enough spaces required between contact plugs and diffusion regions/gates, for example, are ignored in the minimum design rule. As a result, chips are easy to be damaged by electrostatic discharges in a high-integration condition. Obviously, electrostatic discharge is one of main factors to cause deep sub-micron-based ICs damage. Thus, how to enhance the performance of electrostatic discharge protection circuits is a key issue for semiconductor industry to resolve.
FIGS. 1A and 1B are schematic views showing two conventional electrostatic discharge protection circuits. Referring to FIG. 1A, electrostatic charges directed to an input port INP can be discharged to ground Vss through an N-type MOS N1 transistor thereby to protect an internal circuit 10 from damage. Referring to FIG. 1B, another electrostatic discharge protection circuit is shown. In FIG. B, electrostatic charges directed to an input port INP can be discharged not only to ground Vss through an N-type MOS transistor N1, but also to a power source V.sub.DD through a P-type MOS transistor P1, thereby protecting an internal circuit 20 from damage.
Referring to FIG. 2, a schematic, cross-sectional view of the electrostatic discharge protection circuit of FIG. 1A is shown. In FIG. 2, the MOS transistor N1 is formed on a substrate 20 and has a drain 22, a source 24 and a gate 26, wherein the gate 26 is separated from the substrate 20 with a gate oxide layer 25 therebetween. The MOS transistor N1 and the substrate 20 are covered with an insulation layer 28. In the insulation layer 28, first contact plugs 30 and second contact plugs 32 are formed, wherein the first contact plugs 30 electrically connects the drain 22 and an input line I/P while the second contact plugs 32 electrically connects the source 24 and ground Vss.
Referring to FIG. 3, a schematic, top view of the electrostatic discharge protection circuit of FIG. 2 is shown. That is, FIG. 2 is a schematic, cross-sectional view along a dotted line I--I' of FIG. 3. In FIG. 3, solid circles labeled with reference numeral 30 represent the first contact plugs 30 while solid circles labeled with reference numeral 32 represent the second contact plugs 32. The source 24 and the gate 26 all are electrically coupled to ground Vss, and the drains 22 are electrically coupled to the input line I/P as shown in FIG. 1A. A transient current I.sub.1 caused by an electrostatic discharge can be discharged to the drain 22 through the first contact plugs 30 and then to ground Vss through the second contact plugs 32.
However, when a current is unevenly turned on or there exits defects in the structure, the transient current I.sub.1 caused by an electrostatic discharge will collectively flow towards specific local regions having the problems of uneven turn-on and/or detects. Therefore, a great amount of transient current will be generated in the specific local regions to cause high temperatures thereon, and even damage to the internal circuit 10. As a result, the performance of the electrostatic discharge protection circuit is greatly reduced.